1. Field of the Invention
The present invention generally relates to semiconductor device packages and to methods of fabricating semiconductor device packages, and more particularly, the present invention relates to semiconductor device packages having redistribution patterns and to methods of fabricating semiconductor device packages having redistribution patterns.
2. Description of the Related Art
In semiconductor chip packaging, wafer level packages are known in which external terminals, such as metallic solder balls, are distributed in an array over the surface of a semiconductor chip. In fabrication, the formation of the external terminals is carried out at the wafer level, and thereafter the wafer is diced into separate chip packages. Generally, the pads of the semiconductor chip and the external terminals of the chip package are not aligned, and accordingly, a pad redistribution scheme (or rerouting scheme) is needed in which chip pads are electrically redistributed for connection to the external terminals of the package.
FIG. 1 is a schematic plane view of a pad redistribution scheme employed in a conventional wafer level package, and FIGS. 2A and 2B are cross-sectional views taken along lines I-I′ and II-II′ of FIG. 1. A single wafer level package is illustrated, but in manufacture a plurality of such packages are simultaneously formed on a wafer and then separated into individual packages.
Referring collectively to FIGS. 1, 2A and 2B, the wafer level package includes a substrate 1 (e.g., a semiconductor chip), an interlayer dielectric layer 3, chip pads 5, a passivation layer 7, and a lower dielectric layer 9. As illustrated, surface portions of the chip pads 5 are exposed through the passivation layer 7 and the lower dielectric layer 9. Conductive redistribution patterns 11 are formed on the lower dielectric layer 9 so as to electrically connect the chip pads 5 to corresponding ones of solder balls 15. The solder balls 15 are formed in openings contained in an upper dielectric layer 13 which covers the redistribution patterns 11 and the lower dielectric layer 9. In this manner, the chip pads 5 are electrically redistributed in the form of the array defined by the solder balls 15.
Although not shown, the redistribution patterns 11 formed on the lower dielectric layer 9 are made up of signal lines, a power line, and a ground line. As such, in view of the intervening dielectric layer 9, parasitic capacitances are formed between these lines and the internal circuitry (not shown) of the chip or substrate 1. These capacitances are inversely proportional to the thickness 9T of the lower dielectric layer 9.
In order to reduce the RC delay time of the signal lines contained in the redistribution pattern, it is desirable to increase the thickness 9T of the lower dielectric layer 9 to thereby minimize the parasitic capacitance between the signal lines and the substrate 1. However, in order to increase noise immunity characteristics, it is desirable to decrease the thickness 9T of the lower dielectric layer to thereby maximize the parasitic capacitance between the power/ground lines and chip 1. Further, increasing the thickness 9T of the lower dielectric layer 9 may disadvantageously increase physical stresses and cause warping of the wafer during manufacture of the package.